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Proceedings Papers

Copper Plating Process for Through Silicon Via With High Aspect Ratio in Advanced Packaging

Yu Hung Huang, Huei-Huang Lee, Sheng-Jye Hwang, Durn-Yuan Huang

Proc. ASME. InterPACK2009, ASME 2009 InterPACK Conference, Volume 1, 9-14, July 19–23, 2009

Paper No: InterPACK2009-89163

DOI: https://doi.org/10.1115/InterPACK2009-89163

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Topics: Copper, Packaging, Plating, Silicon

Proceedings Papers

Mold Adhesion Force Measurement

Huei-Huang Lee, Sheng-Jye Hwang, Durn-Yuan Huang, Yeong-Jyh Lin

Proc. ASME. InterPACK2007, ASME 2007 InterPACK Conference, Volume 1, 51-58, July 8–12, 2007

Paper No: IPACK2007-33826

DOI: https://doi.org/10.1115/IPACK2007-33826

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Topics: Adhesion, Force measurement, Coatings, Molding, Engineers, Instrumentation, Temperature, Foundry coatings, Surface finishing, Cavities

Proceedings Papers

Simulation of Warpage Considering Both Thermal and Cure Induced Shrinkage During Molding in IC Packaging

Shiang-Yu Teng, Sheng-Jye Hwang

Proc. ASME. InterPACK2005, Advances in Electronic Packaging, Parts A, B, and C, 867-872, July 17–22, 2005

Paper No: IPACK2005-73062

DOI: https://doi.org/10.1115/IPACK2005-73062

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Topics: Integrated circuit packaging, Molding, Shrinkage (Materials), Simulation, Warping, Pressure, Simulation models, Temperature, Thermal expansion

Journal Articles

Simulations of Process-Induced Warpage During IC Encapsulation Process

Shiang-Yu Teng, Sheng-Jye Hwang

J. Electron. Packag. September 2007, 129(3): 307–315.

DOI: https://doi.org/10.1115/1.2753936

Published Online: December 11, 2006

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Topics: Shrinkage (Materials), Simulation, Warping, Temperature

Journal Articles

Three-Dimensional Paddle Shift Modeling for IC Packaging

Chien-Chang Pei, Sheng-Jye Hwang

J. Electron. Packag. September 2005, 127(3): 324–334.

DOI: https://doi.org/10.1115/1.1938986

Published Online: December 2, 2004

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Topics: Computation, Deflection, Flow (Dynamics), Fluid dynamics, Geometry, Integrated circuit packaging, Integrated circuits, Mesh generation, Modeling, Molding

Journal Articles

Prediction of Wire Sweep During the Encapsulation of IC Packaging With Wire Density Effect

Chien-Chang Pei, Sheng-Jye Hwang

J. Electron. Packag. September 2005, 127(3): 335–339.

DOI: https://doi.org/10.1115/1.1939028

Published Online: November 3, 2004

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Topics: Density, Wire, Flow (Dynamics)

Journal Articles

Computer-Aided Design of a TSOP II LOC Package Using Taguchi’s Parameter Design Method to Optimize Mold-Flow Balance

Hung-Lung Lee, Shyang-Jye Chang, Sheng-Jye Hwang, Associate Professor,, Francis Su, S. K. Chen

J. Electron. Packag. June 2003, 125(2): 268–275.

DOI: https://doi.org/10.1115/1.1569957

Published Online: June 10, 2003

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Topics: Computer-aided design, Design, Design methodology, Flow (Dynamics), Taguchi methods, Noise factors, Molding, Packaging, Simulation, Manufacturing

Journal Articles

An Efficient Solution for Wire Sweep Analysis in IC Packaging

Jerry Su, Sheng-Jye Hwang, Associate Professor, Francis Su, Shou-Kang Chen

J. Electron. Packag. March 2003, 125(1): 139–143.

DOI: https://doi.org/10.1115/1.1535447

Published Online: March 14, 2003

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Topics: Wire, Flow (Dynamics), Integrated circuits, Integrated circuit packaging

Journal Articles

Study of P-V-T-C Relation of EMC

Yi-San Chang, Sheng-Jye Hwang, Huei-Huang Lee, Durn-Yuan Huang

J. Electron. Packag. December 2002, 124(4): 371–373.

DOI: https://doi.org/10.1115/1.1498266

Published Online: December 12, 2002

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Topics: Differential scanning calorimetry, Molding, Pressure, Shrinkage (Materials), Temperature, Thermal expansion, Epoxy resins, Chemical kinetics, Viscosity

Journal citation

NARROW

Copper Plating Process for Through Silicon Via With High Aspect Ratio in Advanced Packaging

Mold Adhesion Force Measurement

Simulation of Warpage Considering Both Thermal and Cure Induced Shrinkage During Molding in IC Packaging

Simulations of Process-Induced Warpage During IC Encapsulation Process

Three-Dimensional Paddle Shift Modeling for IC Packaging

Prediction of Wire Sweep During the Encapsulation of IC Packaging With Wire Density Effect

Computer-Aided Design of a TSOP II LOC Package Using Taguchi’s Parameter Design Method to Optimize Mold-Flow Balance

An Efficient Solution for Wire Sweep Analysis in IC Packaging

Study of P-V-T-C Relation of EMC

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