Various methodologies of wire sweep analysis have been introduced to get better prediction and matching the experimental measurements by many researchers. As more and more high pin-count packages (such as BGA, QFP) are used today, efficiency has become an important requirement besides accuracy for software used to predict wire sweep in IC packaging. This study introduces a newly developed wire sweep analysis solution (InPack), not only to meet the need of accuracy, but also enhance the efficiency for actual applications. It combines global flow analysis (C-MOLD) and structure analysis (ANSYS) to become a solution for general wire sweep analysis.

Issue Section:
Technical Papers
Keywords:
integrated circuit packaging, encapsulation, drag, moulding, wires (electric), electronic engineering computing, integrated circuit reliability
Topics:
Wire, Flow (Dynamics), Integrated circuits, Integrated circuit packaging
1.
Han, S., 1994. “A Study on Plastic Encapsulation of Semiconductor Chips,” Cornell Injection Molding Program Technical Report No. 77.
2.
Han, S., and Wang, K. K., 1993. “Analysis of Wire Sweep Related to Encapsulation of Semiconductor Chips,” Chap. X, CIMP Progress Report No. 17.
3.
Han, S., and Wang, K. K., 1993. “A Study on the Effects of Fillers on Wire Sweep Related to Semiconductor Chip Encapsulation,” ASME Winter Annual Meeting.
4.
Han, S., and Wang, K. K., 1995. “Flow Analysis in a Cavity with Leadframe during Semiconductor Chip Encapsulation,” Advances in Electronic Packaging ASME EEP-Vol. 10-1.
5.
C-MOLD Reactive Molding and Microchip Encapsulation Training Guide, C-MOLD Pacific.
6.
Idelchik, I. E., 1994, Handbook of Hydraulic Resistance, CRC Press.
Copyright © 2003
 by ASME
You do not currently have access to this content.