Using detailed finite element models, a fracture analysis of solder bumps and under bump metallurgy (UBM) in flip-chip packages is carried out. Our objective is to identify likely fracture modes and potential delamination sites at or near these microstructural components. In order to study flip-chips, whose dimension spans from sub-micron thickness UBM layers to several millimeters wide package, we have applied a multi-scale finite element analysis (MS-FEA) procedure. In this procedure, initially, deformation of whole thermally loaded package is analyzed. Then, the results are prescribed as the boundary conditions in a very detailed cell model, containing a single solder bump, to investigate micro-deformation surrounding UBM. Using the models with two different scales, accurate stress fields as well as fracture parameters of various interface cracks can be determined. The MS-FEA is ideally suited for the flip-chip packages since they contain many identical solder bumps. A cell model can be repeatedly used to probe stress and fracture behaviors at different locations. The computed results show high stress concentrations near the corners of solder bumps and UBM layers. Based on the energy release rate calculations, solder bumps located near the edge of chip are more likely to fail. However, our results also suggest possible delamination growth at solder bumps near the center of chip. In addition, we have observed increasing energy release rates for longer cracks, which implies a possibility of unstable crack growth.

Issue Section:
Papers on Reliability
Keywords:
flip-chip devices, delamination, integrated circuit reliability, finite element analysis, thermal stress cracking, integrated circuit packaging, fracture mechanics
Topics:
Delamination, Fracture (Materials), Solders, Stress, Fracture (Process), Flip-chip packages, Finite element analysis
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