This paper presents potential application of stainless steel (SS) as a base substrate material for large area multi-chip module-deposited (MCM-D) packaging. Preliminary results on via formation on SS substrates by laser drilling, dielectric coating on SS surface and on via sidewall, via filling for front-to-back interconnects, and subsequent curing of via filling material are reported in this paper. The objective of this DARPA funded MCM-D Consortium is to investigate the feasibility of application of stainless steel materials for large area MCM-D packaging through laboratory prototypes and simulated thin film process. This paper particularly addresses the warpage issues related to via formation, dielectric coating on the substrates, and via filling process after substrates were exposed to temperatures above 130 °C for two hours. The change in process induced warpage was quantified by the simple non-destructive Shadow Moire´ technique. The end objective of this work is to be able to fabricate large area 24 in.×24 in.SS substrates with minimum warpage. The study shows that SS can be a candidate substrate for large area MCM-D packaging. [S1043-7398(00)00702-7]

Issue Section:
Technical Papers
Keywords:
stainless steel, substrates, multichip modules, moire fringes
Topics:
Warping, Coating processes, Packaging, Temperature, Shades and shadows, Stainless steel
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