The increasing trend in power levels and densities leads to the need of design thermal optimization, at either module or system level. A numerical study using finite-volume software was conducted to model the transient thermal behavior of a system including a package dissipating large amounts of power over short time durations. The system is evaluated by choosing the appropriate heat sink for the efficient operation of the device under 100W of constant powering, also to enhance the thermal performance of the enclosure/box containing the test stack-up. The intent of the study is to provide a meaningful understanding and prediction of the high transient powering scenarios. The study focuses on several powering and system design scenarios, identifying the main issues encountered during a normal device operation. The power source dissipates 100W for 2 seconds then is cooled for another 2 seconds. This thermal cycle is likely to occur several times during a normal test-up, and it is the main concern of the manufacturers not to exceed a limit temperature during the device testing operation. The transient trend is further extrapolated analytically to extract the steady state peak temperature values, in order to maintain the device peak temperatures below 120°C. The benefit of the study is related to the possibility to extract the maximum/minimum temperatures for a real test involving a large number of heating-cooling cycles, yet maintaining the initial and peak temperatures within a certain range, for the optimal operation of the device. The flow and heat transfer fields are thoroughly investigated. By using a combination of numerical and analytical study, the thermal performance of the device undergoing infinity of periodic thermal cycles is further predicted.
- Electronic and Photonic Packaging Division
System-Level Transient Thermal Analysis for Performance Optimization of High Power Microelectronics
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Chiriac, VA, Lee, TT, & Chen, HS. "System-Level Transient Thermal Analysis for Performance Optimization of High Power Microelectronics." Proceedings of the ASME 2003 International Electronic Packaging Technical Conference and Exhibition. 2003 International Electronic Packaging Technical Conference and Exhibition, Volume 2. Maui, Hawaii, USA. July 6–11, 2003. pp. 435-442. ASME. https://doi.org/10.1115/IPACK2003-35213
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