This paper describes the two key aspects of via transition optimization methodology: impedance matching and power plane resonance suppression. Ground vias are used to improve the impedance mismatch caused by the via transition and the optimal location of the ground vias at the same time helps to suppress the resonance caused by the cavity effect of the power plane pair. Full-wave electromagnetic simulations were carried out to demonstrate that via transition optimization is able achieve resonance-free high bandwidth operation. Optimal use of ground vias will not only enhance impedance matching but also significantly suppress suppression due to power plane resonance. Test vehicle characterizations were also carried out to demonstrate the impact of ground vias and power plane resonance characteristics on signal integrity.
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ASME 2003 International Electronic Packaging Technical Conference and Exhibition
July 6–11, 2003
Maui, Hawaii, USA
Conference Sponsors:
- Electronic and Photonic Packaging Division
ISBN:
0-7918-3690-8
PROCEEDINGS PAPER
Design Optimization of Via Transitions for Broadband Applications
Albert Chee W. Lu,
Albert Chee W. Lu
Singapore Institute of Manufacturing Technology, Singapore
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Wei Fan,
Wei Fan
Singapore Institute of Manufacturing Technology, Singapore
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Lai L. Wai,
Lai L. Wai
Singapore Institute of Manufacturing Technology, Singapore
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Lin Jin,
Lin Jin
Singapore Institute of Manufacturing Technology, Singapore
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Lee A. Low
Lee A. Low
DSO National Laboratories, Singapore
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Albert Chee W. Lu
Singapore Institute of Manufacturing Technology, Singapore
Wei Fan
Singapore Institute of Manufacturing Technology, Singapore
Lai L. Wai
Singapore Institute of Manufacturing Technology, Singapore
Lin Jin
Singapore Institute of Manufacturing Technology, Singapore
Lee A. Low
DSO National Laboratories, Singapore
Paper No:
IPACK2003-35154, pp. 17-23; 7 pages
Published Online:
January 5, 2009
Citation
Lu, ACW, Fan, W, Wai, LL, Jin, L, & Low, LA. "Design Optimization of Via Transitions for Broadband Applications." Proceedings of the ASME 2003 International Electronic Packaging Technical Conference and Exhibition. 2003 International Electronic Packaging Technical Conference and Exhibition, Volume 1. Maui, Hawaii, USA. July 6–11, 2003. pp. 17-23. ASME. https://doi.org/10.1115/IPACK2003-35154
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