Through-silicon via (TSV), being one of the key enabling technologies for three dimensional (3D) Integrated Circuit (IC) stacking, silicon interposer technology, and advanced wafer level packaging (WLP), has attracted tremendous interest throughout the semiconductor industry. However, limited work addresses TSV reliability issue, and most of the existing reliability studies focus on the thermo-mechanical performance of TSVs in a free-standing wafer, rather than in an integrated package. In this paper, three-dimensional thermomechanical Finite-Element (FE) models with TSVs in both free-standing wafers and 3D integrated packages have been built and analyzed. In addition, Design of Experiments (DOE) based approach has been used to understand the effect of various parameters. Results show that the selection of underfill materials between stacked dies is the most dominating design factor for TSV/microbump reliability.
Reliable Design of TSV in Free-Standing Wafers and 3D Integrated Packages
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Liu, X, Simmons-Matthews, M, Wachtler, KP, & Sitaraman, SK. "Reliable Design of TSV in Free-Standing Wafers and 3D Integrated Packages." Proceedings of the ASME 2011 International Mechanical Engineering Congress and Exposition. Volume 11: Nano and Micro Materials, Devices and Systems; Microsystems Integration. Denver, Colorado, USA. November 11–17, 2011. pp. 903-910. ASME. https://doi.org/10.1115/IMECE2011-65767
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