Research Papers

Mechanical Computing Systems Using Only Links and Rotary Joints

[+] Author and Article Information
Ralph C. Merkle

Institute for Molecular Manufacturing,
Palo Alto, CA 94301
e-mail: ralph@merkle.com

Robert A. Freitas, Jr

Institute for Molecular Manufacturing,
Palo Alto, CA 94301
e-mail: rfreitas@rfreitas.com

Tad Hogg

Institute for Molecular Manufacturing,
Palo Alto, CA 94301
e-mail: tad@imm.org

Thomas E. Moore

Independent Consultant,
White Lake, MI 48383
e-mail: mooreth42@gmail.com

Matthew S. Moses

Independent Consultant,
Lafayette, CO 80026
e-mail: matt.moses@jhu.edu

James Ryley

Independent Consultant,
Los Angeles, CA 90241
e-mail: james@ryley.com

1Corresponding author.

Contributed by the Mechanisms and Robotics Committee of ASME for publication in the JOURNAL OF MECHANISMS AND ROBOTICS. Manuscript received December 19, 2017; final manuscript received August 8, 2018; published online September 17, 2018. Assoc. Editor: Clement Gosselin.

J. Mechanisms Robotics 10(6), 061006 (Sep 17, 2018) (15 pages) Paper No: JMR-17-1426; doi: 10.1115/1.4041209 History: Received December 19, 2017; Revised August 08, 2018

A new model for mechanical computing is demonstrated that requires only two basic parts, links, and rotary joints. These basic parts are combined into two main higher level structures, locks, and balances, and suffice to create all necessary combinatorial and sequential logic required for a Turing-complete computational system. While working systems have yet to be implemented using this new approach, the mechanical simplicity of the systems described may lend themselves better to, e.g., microfabrication, than previous mechanical computing designs. Additionally, simulations indicate that if molecular-scale implementations could be realized, they would be far more energy-efficient than conventional electronic computers.

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Grahic Jump Location
Fig. 1

A 4-bar linkage in two configurations, left-leaning (left) and right-leaning (right)

Grahic Jump Location
Fig. 2

The mobile linkage (left) is free to move, while the nonmobile linkage (right) is static

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Fig. 3

A lock in the (0, 0) position (top), a lock in the (1, 0) position (bottom left), and a lock in the (0,1) position (bottom right). The (1,1) position is prohibited by the linkage geometry. See Fig. 16 for additional discussion.

Grahic Jump Location
Fig. 4

A balance coupled to two locks. The inactive configuration is shown on the left. On the right, Lock0 Input has been activated, followed by activation of the balance input, which in turn activates Out put0.

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Fig. 5

A balance- and lock-based NAND Gate, using dual rail logic (i.e., two-links per bit)

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Fig. 6

A 1-bit full adder, performing the logical operation described in Fig. 7. A table of the schematic symbols used in this drawing is provided in the Appendix (Fig. 26).

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Fig. 7

Logic table for the 1-bit full adder shown in Fig. 6

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Fig. 8

Eight 1-bit full adders (wide blocks) are cascaded using ripple carry. As described in Sec. 4.2, multiple blocks can be cascaded using a four-phase clock. Narrow blocks are shift register cells, which form a delay line that stores portions of the results during computation. The final result appears on the outputs (right side) after two full clock cycles.

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Fig. 9

Left: shift register cell in the (0,0) blank state; center: shift register cell with input (1,0) prior to clock actuation; right: shift register cell with input (1,0) after clock actuation

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Fig. 10

A two-cell shift register (left) shown with a plot of a four-phase clock cycle (right). In this example, the clock signal of cell 1 is driven by clock 1, and the clock signal of cell 2 is driven by clock 2.

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Fig. 11

A suitable multiphase clock signal can be generated mechanically using cams and followers. Here, a four-phase clock signal is generated using four identical cams spaced 90 deg out of phase. The four diagrams at the upper right show the cam at four rotations with only one of the four links. The collection of all four waveforms is shown in the right hand portion of Fig. 10.

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Fig. 12

A 4-cell shift register driven by a four-phase clock, shown at time t = 3/4. The last three cells are set to state 1 and the first cell in the blank state. Animations of this mechanism operating in forward and reverse are available in online.2,3 Solid models available online.4

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Fig. 13

A simple state machine. The main components are highlighted for comparison with Fig. 12. This state machine implements the transition table shown in Fig. 14. A table of the schematic symbols used in this drawing is provided in the Appendix (Fig. 26).

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Fig. 14

Block diagram of a generic Moore machine adapted for a four-phase clock. The state memory is implemented as a chain of shift register cells, similar to those shown in Figs. 8 and 12.

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Fig. 15

State transition diagram and table for the simple state machine of Fig. 13

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Fig. 16

Analyzing lock holding force. In the ideal case (upper left), the lock has two overlapping sets of solutions: θ0=0,θ1≠0 and θ0≠0,θ1=0, with a kinematic branch point [25,26] at θ0=0,θ1=0. Link flexibility can be modeled by replacing one of the links with a spring (lower left). The contour plot shows level sets of spring energy as a function of input angles. In the ideal case, an arbitrarily large force can be locked without affecting the other input. In the more realistic case including link flexibility, a small holding force on one input can hold a large force on the other input.

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Fig. 17

Logic circuitry for read and write operations on a high density memory storage cell

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Fig. 18

A balance- and lock-based Fredkin (CSWAP) gate, using a two-link per bit design (i.e., dual rail logic). This mechanical logic gate is logically and physically reversible. The logic table implemented is shown in Fig. 19.

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Fig. 19

Logic table for reversible Fredkin (CSWAP) gate (see Fig. 18). Identical portions of the inputs and outputs are highlighted in the same color as a guide for the eye.

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Fig. 20

On the left, two concepts for inputting signals to the mechanical computer are shown; two concepts for outputting signals are shown on the right

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Fig. 21

Asynchronous, noisy signals (such as from a mechanical sensor) can be conditioned so that synchronous dual rail mechanical logic gates can process them

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Fig. 22

Schematic layout for a simple test mechanism containing a balance, two locks, and signal routing mechanisms

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Fig. 23

Computer aided design model of the test system shown in Fig. 22 implemented with 3D-printed components assembled over standard hardware and pegboard. Solid models available online.4

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Fig. 24

A flexure-based implementation of the system shown in Fig. 22, made of two or three stacked layers (a second outer layer can be added to make a three-layer assembly for increased rigidity). Interlayer bonds are shown as dark dots in the lower right image. Solid models available online.4

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Fig. 25

Part of a molecular mechanical logic gate. This molecular machine consists of 120,695 atoms, 87,595 carbon and 33,100 hydrogen, and occupies a volume of about 27 nm × 32 nm × 7 nm. The nine rigid links are connected to each other via a pair of rotary joints. Atomic structure file available online.4

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Fig. 26

Schematic symbols for mechanical linkage logic components, including the lock, two versions of a balance, and mechanisms for routing signals

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Fig. 27

A balance- and lock-based NOR Gate, using a two-link per bit input/output design

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Fig. 28

A balance- and lock-based XOR gate, using a two-link per bit input/output design



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